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» Review of Affective Computing
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HPCA
2005
IEEE
16 years 7 months ago
Software Directed Issue Queue Power Reduction
The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling sy...
Antonio González, Jaume Abella, Michael F. ...
HPCA
2004
IEEE
16 years 7 months ago
Reducing the Scheduling Critical Cycle Using Wakeup Prediction
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...
Todd E. Ehrhart, Sanjay J. Patel
HPCA
2003
IEEE
16 years 7 months ago
Reconsidering Complex Branch Predictors
To sustain instruction throughput rates in more aggressively clocked microarchitectures, microarchitects have incorporated larger and more complex branch predictors into their des...
Daniel A. Jiménez
HPCA
2001
IEEE
16 years 7 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
CHI
2004
ACM
16 years 7 months ago
Exploring PC-telephone convergence with the enhanced telephony prototype
Industry trends suggest that the PC and telephone user experiences will converge over the next several years. This convergence raises important questions for the HCI community: ho...
Jonathan J. Cadiz, Attila Narin, Gavin Jancke, Ano...