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2003
IEEE
15 years 11 months ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
DFT
2003
IEEE
132views VLSI» more  DFT 2003»
15 years 11 months ago
Level-Hybrid Optoelectronic TESH Interconnection Network
This paper discusses a hybrid optoelectronic scheme for a new interconnection network, "Tori connected mESHes (TESH)". The major features of TESH are the following: it i...
Vijay K. Jain, Glenn H. Chapman
DFT
2003
IEEE
99views VLSI» more  DFT 2003»
15 years 11 months ago
Dependability Analysis of CAN Networks: An Emulation-Based Approach
1 Today many safety-critical applications are based on distributed systems where several computing nodes exchange information via suitable network interconnections. An example of t...
J. Pérez, Matteo Sonza Reorda, Massimo Viol...
DFT
2003
IEEE
142views VLSI» more  DFT 2003»
15 years 11 months ago
Exploiting Instruction Redundancy for Transient Fault Tolerance
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
Toshinori Sato
HICSS
2003
IEEE
156views Biometrics» more  HICSS 2003»
15 years 11 months ago
Developing Video Services for Mobile Users
Video information, image processing and computer vision techniques are developing rapidly nowadays because of the availability of acquisition, processing and editing tools, which ...
Mohamed Ahmed, Roger Impey, Ahmed Karmouch
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