7262 search results - page 1273 / 1453 » Reversible Computer Hardware |
193
click to vote
WMPI
2004
ACM
15 years 12 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
163
click to vote
WMPI
2004
ACM
15 years 12 months ago
2004
ACM
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...
189
click to vote
WMPI
2004
ACM
15 years 12 months ago
2004
ACM
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
146
click to vote
WMPI
2004
ACM
15 years 12 months ago
2004
ACM
Abstract. Recent research indicates that prediction-based coherence optimizations offer substantial performance improvements for scientific applications in distributed shared memor...
175
click to vote
WMPI
2004
ACM
15 years 12 months ago
2004
ACM
Abstract. In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software ...