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ISCAS
2006
IEEE
86views Hardware» more  ISCAS 2006»
16 years 15 days ago
Fast timing analysis of plane circuits via two-layer CNN-based modeling
Abstract— A fast timing analysis of plane circuits via two-layer CNNbased modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boar...
Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifum...
ISCAS
2006
IEEE
112views Hardware» more  ISCAS 2006»
16 years 15 days ago
Towards an optimised VLSI design algorithm for the constant matrix multiplication problem
The efficient design of multiplierless implementa- The goal is to find the optimal sub-expressions across all N dot tions of constant matrix multipliers is challenged by the huge p...
Andrew Kinane, Valentin Muresan, Noel E. O'Connor
LCN
2006
IEEE
16 years 15 days ago
Efficient Packet Processing in User-Level OSes: A Study of UML
Network server consolidation has become popular through recent virtualization technology that builds secure, isolated network systems on shared hardware. One of the virtualization...
Younggyun Koh, Calton Pu, Sapan Bhatia, Charles Co...
LCN
2006
IEEE
16 years 15 days ago
Practical Evaluation of the Performance Impact of Security Mechanisms in Sensor Networks
Security has become a major concern for many realworld applications for wireless sensor networks (WSN). In this domain, many security solutions have been proposed. Usually, all th...
Martin Passing, Falko Dressler
TAICPART
2006
IEEE
131views Education» more  TAICPART 2006»
16 years 14 days ago
Bogor: A Flexible Framework for Creating Software Model Checkers
Model checking has proven to be an effective technology for verification and debugging in hardware and more recently in software domains. With the proliferation of multicore arch...
Robby, Matthew B. Dwyer, John Hatcliff
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