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VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
16 years 6 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
VLSID
2002
IEEE
138views VLSI» more  VLSID 2002»
16 years 6 months ago
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
Haris Lekatsas, Jörg Henkel
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
16 years 6 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
ICALP
2009
Springer
16 years 6 months ago
On Regular Temporal Logics with Past,
The IEEE standardized Property Specification Language, PSL for short, extends the well-known linear-time temporal logic LTL with so-called semi-extended regular expressions. PSL an...
Christian Dax, Felix Klaedtke, Martin Lange
3DIM
2007
IEEE
16 years 6 months ago
Automatic Pose Estimation for Range Images on the GPU
Object pose (location and orientation) estimation is a common task in many computer vision applications. Although many methods exist, most algorithms need manual initialization ...
Marcel Germann, Michael D. Breitenstein, In Kyu Pa...
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