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VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
16 years 7 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
VLSID
2009
IEEE
115views VLSI» more  VLSID 2009»
16 years 7 months ago
Efficient Techniques for Directed Test Generation Using Incremental Satisfiability
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...
Prabhat Mishra, Mingsong Chen
VLSID
2009
IEEE
139views VLSI» more  VLSID 2009»
16 years 7 months ago
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
Tameesh Suri, Aneesh Aggarwal
CAV
2009
Springer
135views Hardware» more  CAV 2009»
16 years 7 months ago
Sliding Window Abstraction for Infinite Markov Chains
Window Abstraction for Infinite Markov Chains Thomas A. Henzinger1 , Maria Mateescu1 , and Verena Wolf1,2 1 EPFL, Switzerland 2 Saarland University, Germany Abstract. We present an...
Thomas A. Henzinger, Maria Mateescu, Verena Wolf
CAV
2009
Springer
184views Hardware» more  CAV 2009»
16 years 7 months ago
Monotonic Partial Order Reduction: An Optimal Symbolic Partial Order Reduction Technique
Abstract. We present a new technique called Monotonic Partial Order Reduction (MPOR) that effectively combines dynamic partial order reduction with symbolic state space exploration...
Vineet Kahlon, Chao Wang, Aarti Gupta
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