7262 search results - page 1222 / 1453 » Reversible Computer Hardware |
162
click to vote
DAC
2007
ACM
16 years 7 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
148
click to vote
DAC
2007
ACM
16 years 7 months ago
2007
ACM
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
131
click to vote
DAC
2007
ACM
16 years 7 months ago
2007
ACM
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case condit...
178
click to vote
DAC
2007
ACM
16 years 7 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
159
click to vote
DAC
2007
ACM
16 years 7 months ago
2007
ACM
Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance,...