7262 search results - page 1190 / 1453 » Reversible Computer Hardware |
164
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ISLPED
2003
ACM
15 years 11 months ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
164
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ISPD
2003
ACM
15 years 11 months ago
2003
ACM
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
168
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
Abstract—This paper addresses the problem of execution time estimation for tasks in a software pipeline independent of the application structure or the underlying architecture. A...
125
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ISCA
2010
IEEE
15 years 11 months ago
2010
IEEE
The recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread perfor...
174
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ISCA
2010
IEEE
15 years 11 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...