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IPPS
2000
IEEE
15 years 11 months ago
The Memory Bandwidth Bottleneck and its Amelioration by a Compiler
As the speed gap between CPU and memory widens, memory hierarchy has become the primary factor limiting program performance. Until now, the principal focus of hardware and softwar...
Chen Ding, Ken Kennedy
IPPS
2000
IEEE
15 years 11 months ago
Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
Diana Hecht, Constantine Katsinis
IPPS
2000
IEEE
15 years 11 months ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
IPPS
2000
IEEE
15 years 11 months ago
Image Layer Decomposition for Distributed Real-Time Rendering on Clusters
We propose a novel work partitioning technique, Image Layer Decomposition (ILD), designed specifically to support distributed real-time rendering on commodity clusters. ILD has s...
Thu D. Nguyen, John Zahorjan
PRDC
2000
IEEE
15 years 11 months ago
Enforcing synchronous system properties on top of timed systems
A synchronous system model is a simple yet powerful distributed system model that reduces the complexity of the design and implementation of dependable distributed applications. H...
Christof Fetzer
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