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ISLPED
2004
ACM
88views Hardware» more  ISLPED 2004»
16 years 3 days ago
Architecting voltage islands in core-based system-on-a-chip designs
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu ...
SAC
2004
ACM
16 years 3 days ago
L0 buffer energy optimization through scheduling and exploration
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
Murali Jayapala, Tom Vander Aa, Francisco Barat, G...
SIGMETRICS
2004
ACM
141views Hardware» more  SIGMETRICS 2004»
16 years 3 days ago
Spatio-temporal available bandwidth estimation with STAB
We study the problem of locating in space and over time a network path’s tight link, that is the link with the least available bandwidth on the path. Tight link localization ben...
Vinay J. Ribeiro, Rudolf H. Riedi, Richard G. Bara...
SPAA
2004
ACM
16 years 3 days ago
DCAS is not a silver bullet for nonblocking algorithm design
Despite years of research, the design of efficient nonblocking algorithms remains difficult. A key reason is that current shared-memory multiprocessor architectures support only s...
Simon Doherty, David Detlefs, Lindsay Groves, Chri...
155
Voted
WMPI
2004
ACM
16 years 3 days ago
A case for multi-level main memory
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
Magnus Ekman, Per Stenström
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