Sciweavers

7262 search results - page 1097 / 1453
» Reversible Computer Hardware
Sort
View
CODES
2007
IEEE
16 years 1 months ago
Combined approach to system level performance analysis of embedded systems
Compositional approaches to system-level performance analysis have shown great flexibility and scalability in the design of heterogeneous systems. These approaches often assume c...
Simon Künzli, Arne Hamann, Rolf Ernst, Lothar...
DSN
2007
IEEE
16 years 1 months ago
How Do Mobile Phones Fail? A Failure Data Analysis of Symbian OS Smart Phones
While the new generation of hand-held devices, e.g., smart phones, support a rich set of applications, growing complexity of the hardware and runtime environment makes the devices...
Marcello Cinque, Domenico Cotroneo, Zbigniew Kalba...
DSN
2007
IEEE
16 years 1 months ago
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
Viswanathan Subramanian, Mikel Bezdek, Naga Durga ...
DSN
2007
IEEE
16 years 1 months ago
Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays
Programmable logic arrays (PLA), which can implement arbitrary logic functions in a two-level logic form, are promising as platforms for nanoelectronic logic due to their highly r...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
FCCM
2007
IEEE
129views VLSI» more  FCCM 2007»
16 years 1 months ago
Automatic On-chip Memory Minimization for Data Reuse
FPGA-based computing engines have become a promising option for the implementation of computationally intensive applications due to high flexibility and parallelism. However, one...
Qiang Liu, George A. Constantinides, Konstantinos ...
« Prev « First page 1097 / 1453 Last » Next »