7262 search results - page 1096 / 1453 » Reversible Computer Hardware |
228
click to vote
SMI
2008
IEEE
16 years 1 months ago
2008
IEEE
In this paper, we introduce a parallel numerical scheme, the lattice Boltzmann method, to shape modeling applications. The motivation of using this originally-designed fluid dyna...
147
click to vote
TRIDENTCOM
2008
IEEE
16 years 1 months ago
2008
IEEE
This paper presents the setup of a testbed developed for the fast evaluation of RFID systems in two frequency domains. At the one hand the 13.56 MHz and at the other hand the 868 ...
148
click to vote
ARITH
2007
IEEE
16 years 1 months ago
2007
IEEE
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
170
click to vote
ARITH
2007
IEEE
16 years 1 months ago
2007
IEEE
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
151
click to vote
ARITH
2007
IEEE
16 years 1 months ago
2007
IEEE
The draft revision of the IEEE Standard for FloatingPoint Arithmetic (IEEE P754) includes a definition for decimal floating-point (FP) in addition to the widely used binary FP s...