Sciweavers

7262 search results - page 1063 / 1453
» Reversible Computer Hardware
Sort
View
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
16 years 8 hour ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
EWSN
2010
Springer
15 years 12 months ago
Wiselib: A Generic Algorithm Library for Heterogeneous Sensor Networks
One unfortunate consequence of the success story of wireless sensor networks (WSNs) in separate research communities is an evergrowing gap between theory and practice. Even though ...
Tobias Baumgartner, Ioannis Chatzigiannakis, S&aac...
DATE
2010
IEEE
113views Hardware» more  DATE 2010»
15 years 12 months ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
ISCA
2010
IEEE
204views Hardware» more  ISCA 2010»
15 years 12 months ago
Energy proportional datacenter networks
Numerous studies have shown that datacenter computers rarely operate at full utilization, leading to a number of proposals for creating servers that are energy proportional with r...
Dennis Abts, Michael R. Marty, Philip M. Wells, Pe...
FCCM
2002
IEEE
126views VLSI» more  FCCM 2002»
15 years 11 months ago
Hyperspectral Image Compression on Reconfigurable Platforms
NASA’s satellites currently do not make use of advanced image compression techniques during data transmission to earth because of limitations in the available platforms. With th...
Thomas W. Fry, Scott Hauck
« Prev « First page 1063 / 1453 Last » Next »