Sciweavers

7262 search results - page 1059 / 1453
» Reversible Computer Hardware
Sort
View
ESTIMEDIA
2007
Springer
16 years 28 days ago
Leveraging Predicated Execution for Multimedia Processing
—Modern compression standards such as H.264, DivX, or VC-1 provide astonishing quality at the costs of steadily increasing processing requirements. Therefore, efficient solution...
Dietmar Ebner, Florian Brandner, Andreas Krall
IESS
2007
Springer
120views Hardware» more  IESS 2007»
16 years 27 days ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
IPPS
2006
IEEE
16 years 24 days ago
Compatible phase co-scheduling on a CMP of multi-threaded processors
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous MultiThreaded (SMT) cores for general purpose systems. The most prominent use o...
Ali El-Moursy, R. Garg, David H. Albonesi, Sandhya...
ACL2
2006
ACM
16 years 22 days ago
A verifying core for a cryptographic language compiler
A verifying compiler is one that emits both object code and a proof of correspondence between object and source code.1 We report the use of ACL2 in building a verifying compiler f...
Lee Pike, Mark Shields, John Matthews
ISPD
2006
ACM
175views Hardware» more  ISPD 2006»
16 years 22 days ago
mPL6: enhanced multilevel mixed-size placement
The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently pr...
Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kent...
« Prev « First page 1059 / 1453 Last » Next »