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DSN
2008
IEEE
16 years 1 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
IPPS
2008
IEEE
16 years 1 months ago
Balancing HPC applications through smart allocation of resources in MT processors
Abstract—Many studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1...
Carlos Boneti, Roberto Gioiosa, Francisco J. Cazor...
IPPS
2008
IEEE
16 years 1 months ago
Lattice Boltzmann simulation optimization on leading multicore platforms
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of searchbased performance optimizatio...
Samuel Williams, Jonathan Carter, Leonid Oliker, J...
IPPS
2008
IEEE
16 years 1 months ago
Qthreads: An API for programming with millions of lightweight threads
Large scale hardware-supported multithreading, an attractive means of increasing computational power, benefits significantly from low per-thread costs. Hardware support for ligh...
Kyle B. Wheeler, Richard C. Murphy, Douglas Thain
ASAP
2007
IEEE
135views Hardware» more  ASAP 2007»
16 years 1 months ago
An Application Specific Memory Characterization Technique for Co-processor Accelerators
Commodity accelerator technologies including reconfigurable devices provide an order of magnitude performance improvement compared to mainstream microprocessor systems. A number o...
Sadaf R. Alam, Jeffrey S. Vetter, Melissa C. Smith
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