34 search results - page 6 / 7 » Reusing Scan Chains for Test Pattern Decompression |
186
click to vote
DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
164
click to vote
TCAD
1998
15 years 5 months ago
1998
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
174
click to vote
TC
2008
15 years 5 months ago
2008
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
187
click to vote
ATS
2005
IEEE
15 years 11 months ago
2005
IEEE
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...
157
click to vote
VTS
2003
IEEE
15 years 11 months ago
2003
IEEE
—We present a dictionary-based test data compression approach for reducing test data volume and testing time in SOCs. The proposed method is based on the use of a small number of...