2778 search results - page 99 / 556 » Reuse Technique in Hardware Design |
175
click to vote
EUROMICRO
2005
IEEE
15 years 11 months ago
2005
IEEE
Many component models have been proposed to address the challenge of reducing software development time and costs. Such models often offer similar functionality. We study how deve...
166
click to vote
ISLPED
2005
ACM
15 years 11 months ago
2005
ACM
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
171
click to vote
ICCD
1995
IEEE
15 years 9 months ago
1995
IEEE
Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware desig...
154
click to vote
ASPDAC
2006
ACM
16 years 5 days ago
2006
ACM
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
137
click to vote
ASPDAC
2006
ACM
16 years 5 days ago
2006
ACM
Abstract— With technology scaling, on-chip power densities are growing steadily, leading to the point where temperature has become an important consideration in the design of ele...