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DATE
2005
IEEE
112views Hardware» more  DATE 2005»
15 years 11 months ago
TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques
In this paper we present arithmetic real-coded variation operators tailored for time slot and turn optimization on TDMA-scheduled resources with evolutionary algorithms. Our opera...
Arne Hamann, Rolf Ernst
DSD
2003
IEEE
107views Hardware» more  DSD 2003»
15 years 11 months ago
DYNORA: A New Caching Technique
Cache design for high performance computing requires the realization of two seemingly disjoint goals of higher hit ratios at reduced access times. Recent research advocates the us...
P. Srivatsan, P. B. Sudarshan, P. P. Bhaskaran
ICCAD
1998
IEEE
107views Hardware» more  ICCAD 1998»
15 years 10 months ago
Techniques for energy minimization of communication pipelines
The performance of many modern computer and communication systems is dictated by latency of communication pipelines. At the same time, power consumption is often another limiting ...
Gang Qu, Miodrag Potkonjak
MICRO
1993
IEEE
128views Hardware» more  MICRO 1993»
15 years 10 months ago
Techniques for extracting instruction level parallelism on MIMD architectures
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
Gary S. Tyson, Matthew K. Farrens
DSD
2010
IEEE
171views Hardware» more  DSD 2010»
15 years 4 months ago
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
Jiri Balcarek, Petr Fiser, Jan Schmidt