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» Reuse Technique in Hardware Design
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ICCD
2002
IEEE
110views Hardware» more  ICCD 2002»
16 years 3 months ago
Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques
Practical approaches for on-chip inductance extraction to obtain a sparse, stable and accurate inverse inductance matrix K are proposed. The novelty of our work is in using circui...
Haitian Hu, Sachin S. Sapatnekar
DSD
2009
IEEE
111views Hardware» more  DSD 2009»
16 years 28 days ago
Robustness Check for Multiple Faults Using Formal Techniques
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
Stefan Frehse, Görschwin Fey, André S&...
ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
15 years 11 months ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
MTV
2007
IEEE
166views Hardware» more  MTV 2007»
16 years 13 days ago
Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits
Abstract—Abstract models of analog/mixed-signal (AMS) circuits can be used for formal verification and system-level simulation. The difficulty of creating these models preclude...
Scott Little, Alper Sen, Chris J. Myers
DATE
2006
IEEE
95views Hardware» more  DATE 2006»
16 years 7 days ago
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
The ever increasing usage of microprocessor devices is sustained by a high volume production that in turn requires a high production yield, backed by a controlled process. Fault d...
Paolo Bernardi, Ernesto Sánchez, Massimilia...