2778 search results - page 88 / 556 » Reuse Technique in Hardware Design |
144
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
— Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on ...
150
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ASYNC
2005
IEEE
15 years 11 months ago
2005
IEEE
A Globally Asynchronous - Locally Synchronous (GALS) technique for application in wireless communication systems is proposed and evaluated. The GALS wrappers are based on a reques...
148
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DATE
2005
IEEE
15 years 11 months ago
2005
IEEE
Linear Pseudo-Boolean Optimization (PBO) is a widely used modeling framework in Electronic Design Automation (EDA). Due to significant advances in Boolean Satisfiability (SAT), ...
169
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CODES
2002
IEEE
15 years 11 months ago
2002
IEEE
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
132
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ASPDAC
2005
ACM
15 years 8 months ago
2005
ACM
— In this paper we present a scheme for reducing the amount of synchronization overhead needed between components, after HW/SW partitioning, to preserve the original control flo...