2778 search results - page 87 / 556 » Reuse Technique in Hardware Design |
127
click to vote
ISQED
2008
IEEE
16 years 17 days ago
2008
IEEE
In multi-core processors there are several ways to pair a thread to a particular core. These load-balancing techniques result in a quite different power, performance and thermal b...
139
click to vote
DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we present a novel multigrid-based technique for power/ground mesh area optimization subject to reliability constraints. The multigrid-based technique is applied to...
155
click to vote
DATE
2000
IEEE
15 years 10 months ago
2000
IEEE
As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem f...
155
click to vote
FPL
2008
Springer
15 years 7 months ago
2008
Springer
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
176
click to vote
ICCAD
1996
IEEE
15 years 10 months ago
1996
IEEE
This paper presents a tutorial on mixed-signal testing. Our focus is on testing the analog portion of the mixed-signal device, as the digital portion is handled in the usual way. ...