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» Reuse Technique in Hardware Design
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PLDI
2009
ACM
16 years 28 days ago
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. M...
IPPS
2006
IEEE
16 years 5 days ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
ENTCS
2010
113views more  ENTCS 2010»
15 years 6 months ago
Geometry of Synthesis II: From Games to Delay-Insensitive Circuits
This paper extends previous work on the compilation of higher-order imperative languages into digital circuits [4]. We introduce concurrency, an essential feature in the context o...
Dan R. Ghica, Alex Smith
CEEMAS
2001
Springer
15 years 10 months ago
MAS Oriented Patterns
Multiagent systems (MAS) are spreading, in the academic world as well as in industry. Nevertheless, MAS design is still a problem. The agent community now has some experience. So, ...
Sylvain Sauvage
DATE
2004
IEEE
133views Hardware» more  DATE 2004»
15 years 10 months ago
Channel Decoder Architecture for 3G Mobile Wireless Terminals
Channel coding is a key element of any digital wireless communication system since it minimizes the effects of noise and interference on the transmitted signal. In thirdgeneration...
Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn