2778 search results - page 75 / 556 » Reuse Technique in Hardware Design |
160
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VTS
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper presents a new fault-tolerance technique for cache memories. Current fault-tolerance techniques for caches are limited either by the number of faults that can be tolera...
172
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CASES
2005
ACM
15 years 8 months ago
2005
ACM
Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increa...
143
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FPL
2010
Springer
15 years 4 months ago
2010
Springer
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the to...
156
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FPL
2001
Springer
15 years 10 months ago
2001
Springer
Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its eff...
141
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ISSS
1995
IEEE
15 years 9 months ago
1995
IEEE
We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it ...