2778 search results - page 71 / 556 » Reuse Technique in Hardware Design |
166
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CASES
2010
ACM
15 years 3 months ago
2010
ACM
3-D circuit-level integration is a chip fabrication technique in which two or more dies are stacked and combined into a single circuit through the use of vertical electroconductiv...
164
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
187
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KBSE
2010
IEEE
15 years 4 months ago
2010
IEEE
Scientists today conduct new research via software-based experimentation and validation in a host of disciplines, including materials science, life sciences, astronomy, and physic...
140
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DATE
2010
IEEE
15 years 10 months ago
2010
IEEE
Model checking techniques are promising for automated generation of directed tests. However, due to the prohibitively large time and resource requirements, conventional model chec...
170
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AOSD
2009
ACM
16 years 28 days ago
2009
ACM
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...