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ITC
1995
IEEE
124views Hardware» more  ITC 1995»
15 years 9 months ago
An Experimental Chip to Evaluate Test Techniques: Experiment Results
This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and tes...
Siyad C. Ma, Piero Franco, Edward J. McCluskey
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures
Abstract-- We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency ...
Sushu Zhang, Karam S. Chatha
ICC
2007
IEEE
121views Communications» more  ICC 2007»
16 years 13 days ago
A Real-Time Hardware-Based Scheduler For Next-Generation Optical Burst Switches
– Optical burst switching (OBS) is a promising technique for next-generation optical switching networks. In traditional OBS, an entire burst is discarded when all output waveleng...
Muhammad T. Anan, Ghulam Chaudhry
IEEEARES
2006
IEEE
16 years 4 days ago
Securing DNS Services through System Self Cleansing and Hardware Enhancements
-- Domain Name Systems (DNS) provide the mapping between easily-remembered host names and their IP addresses. Popular DNS implementations however contain vulnerabilities that are e...
Yih Huang, David Arsenault, Arun Sood
DRM
2004
Springer
15 years 11 months ago
Attacks and risk analysis for hardware supported software copy protection systems
Recently, there is a growing interest in the research community to use tamper-resistant processors for software copy protection. Many of these tamper-resistant systems rely on a s...
Weidong Shi, Hsien-Hsin S. Lee, Chenghuai Lu, Tao ...