2778 search results - page 65 / 556 » Reuse Technique in Hardware Design |
146
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IPPS
2007
IEEE
16 years 12 days ago
2007
IEEE
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
154
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ASAP
2006
IEEE
15 years 8 months ago
2006
IEEE
This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. I...
166
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FPL
2003
Springer
15 years 11 months ago
2003
Springer
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
178
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CHARME
1999
Springer
15 years 10 months ago
1999
Springer
Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a my...
135
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...