2778 search results - page 486 / 556 » Reuse Technique in Hardware Design |
168
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ISCA
2010
IEEE
15 years 11 months ago
2010
IEEE
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
154
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip...
190
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USENIX
1993
15 years 7 months ago
1993
In teaching operating systems at an undergraduate level, we believe that it is important to provide a project that is realistic enough to show how real operating systems work, yet...
176
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ICCAD
2009
IEEE
15 years 4 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
136
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GRAPHITE
2005
ACM
15 years 12 months ago
2005
ACM
Drawing on paper is an experience which is still unmatched by any input device for drawing into a computer in terms of accuracy, dexterity and general pleasantness of use. This pa...