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» Reuse Technique in Hardware Design
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FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
16 years 15 days ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
ASPDAC
2006
ACM
155views Hardware» more  ASPDAC 2006»
16 years 9 days ago
Delay defect screening for a 2.16GHz SPARC64 microprocessor
This paper presents a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A nonrobust delay test is used while each test vector is compacted to...
Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hito...
MOBICOM
2006
ACM
16 years 9 days ago
Using packet probes for available bandwidth estimation: a wireless testbed experience
Evaluating available bandwidth estimation methods requires a malleable MAC protocol implementation, precise MAC layer packet timing measurements, and the ability to create control...
Mesut Ali Ergin, Marco Gruteser
SIGMETRICS
2006
ACM
16 years 9 days ago
Stardust: tracking activity in a distributed storage system
Performance monitoring in most distributed systems provides minimal guidance for tuning, problem diagnosis, and decision making. Stardust is a monitoring infrastructure that repla...
Eno Thereska, Brandon Salmon, John D. Strunk, Matt...
ISLPED
2004
ACM
108views Hardware» more  ISLPED 2004»
15 years 11 months ago
SEPAS: a highly accurate energy-efficient branch predictor
Designers have invested much effort in developing accurate branch predictors with short learning periods. Such techniques rely on exploiting complex and relatively large structure...
Amirali Baniasadi, Andreas Moshovos