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» Reuse Technique in Hardware Design
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ASPLOS
2008
ACM
15 years 8 months ago
Adapting to intermittent faults in multicore systems
Future multicore processors will be more susceptible to a variety of hardware failures. In particular, intermittent faults, caused in part by manufacturing, thermal, and voltage v...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
ICCD
2004
IEEE
101views Hardware» more  ICCD 2004»
16 years 3 months ago
Increasing Processor Performance Through Early Register Release
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register file...
Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kan...
MICRO
2009
IEEE
507views Hardware» more  MICRO 2009»
16 years 1 months ago
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
Phase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-effective and power-efficient manner. However, PCM cells can endure on...
Moinuddin K. Qureshi, John Karidis, Michele France...
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
16 years 11 days ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
SENSYS
2004
ACM
15 years 11 months ago
Simulating the power consumption of large-scale sensor network applications
Developing sensor network applications demands a new set of tools to aid programmers. A number of simulation environments have been developed that provide varying degrees of scala...
Victor Shnayder, Mark Hempstead, Bor-rong Chen, Ge...