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» Reuse Technique in Hardware Design
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DAC
2002
ACM
16 years 7 months ago
Scheduler-based DRAM energy management
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
Victor Delaluz, Anand Sivasubramaniam, Mahmut T. K...
CGO
2009
IEEE
16 years 1 months ago
Scenario Based Optimization: A Framework for Statically Enabling Online Optimizations
Abstract—Online optimization allows the continuous restructuring and adaptation of an executing application using live information about its execution environment. The further ad...
Jason Mars, Robert Hundt
IPCCC
2006
IEEE
16 years 11 days ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
VISUALIZATION
2005
IEEE
15 years 12 months ago
Build-by-Number: Rearranging the Real World to Visualize Novel Architectural Spaces
We present Build-by-Number, a technique for quickly designing architectural structures that can be rendered photorealistically at interactive rates. We combine image-based capturi...
Daniel R. Bekins, Daniel G. Aliaga
SIGGRAPH
1996
ACM
15 years 10 months ago
Technologies for Augmented Reality Systems: Realizing Ultrasound-Guided Needle Biopsies
We present a real-time stereoscopic video-see-through augmented reality (AR) system applied to the medical procedure known as ultrasound-guided needle biopsy of the breast. The AR...
Andrei State, Mark A. Livingston, William F. Garre...