2778 search results - page 466 / 556 » Reuse Technique in Hardware Design |
193
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MICRO
2007
IEEE
16 years 19 days ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
164
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ISPD
2003
ACM
15 years 11 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
162
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...
182
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CF
2007
ACM
15 years 10 months ago
2007
ACM
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
153
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ISPD
2007
ACM
15 years 8 months ago
2007
ACM
In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for...