2778 search results - page 465 / 556 » Reuse Technique in Hardware Design |
164
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ASPDAC
1995
ACM
15 years 10 months ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
184
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ISCA
2008
IEEE
15 years 6 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
171
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
169
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ISCA
2009
IEEE
16 years 1 months ago
2009
IEEE
Recent research advocates memory streaming techniques to alleviate the performance bottleneck caused by the high latencies of off-chip memory accesses. Temporal memory streaming r...
191
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ISCA
2009
IEEE
16 years 1 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...