2778 search results - page 459 / 556 » Reuse Technique in Hardware Design |
194
click to vote
VALUETOOLS
2006
ACM
16 years 10 days ago
2006
ACM
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
166
click to vote
MICRO
2005
IEEE
15 years 12 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
151
click to vote
FP
1989
15 years 10 months ago
1989
This paper reports an explanation of an intricate algorithm in the terms of a potentially mechanisable rigorous-development method. It uses notations and techniques of Sheeran 1] ...
150
click to vote
ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
Physical synthesis optimizations and engineering change orders typically change the locations of cells, resize cells or add more cells to the design after global placement. Unfort...
150
click to vote
AAAI
2004
15 years 7 months ago
2004
A wide variety of techniques for visual navigation using robot-mounted cameras have been described over the past several decades, yet adoption of optical flow navigation technique...