2778 search results - page 458 / 556 » Reuse Technique in Hardware Design |
309
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DATE
2011
IEEE
14 years 10 months ago
2011
IEEE
In order to meet performance/low energy/integration requirements, parallel architectures (multithreaded cores and multi-cores) are more and more considered in the design of embedd...
190
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TEI
2012
ACM
14 years 1 months ago
2012
ACM
Existing 3D sketching methods typically allow the user to draw in empty space which is imprecise and lacks tactile feedback. We introduce a shape-stamping interface where users ca...
183
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...
178
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CODES
2008
IEEE
16 years 26 days ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
152
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ISCA
2006
IEEE
16 years 12 days ago
2006
IEEE
The key to high performance in Simultaneous Multithreaded (SMT) processors lies in optimizing the distribution of shared resources to active threads. Existing resource distributio...