2778 search results - page 44 / 556 » Reuse Technique in Hardware Design |
149
Voted
DAC
2001
ACM
16 years 7 months ago
2001
ACM
Currently, hardware intellectual property (IP) is delivered at vels of abstraction: hard, firm, and soft. In order to further enhance performance, efficiency, and flexibility of I...
150
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DATE
2005
IEEE
15 years 11 months ago
2005
IEEE
— Sharing IP blocks in today’s competitive market poses significant high security risks. Creators and owners of IP designs want assurances that their content will not be illeg...
194
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ICCAD
2010
IEEE
15 years 4 months ago
2010
IEEE
1In this paper, we will present an effective layout method for analog circuits. We consider symmetry constraint, common centroid constraint, device merging and device clustering du...
174
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FPL
2006
Springer
15 years 9 months ago
2006
Springer
Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA i...
129
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ASPDAC
2008
ACM
15 years 8 months ago
2008
ACM
- In multi-layered power/ground (P/G) networks, to connect the whole network together, vertical vias are usually placed at intersections between metal wires of adjoining layers. In...