2778 search results - page 400 / 556 » Reuse Technique in Hardware Design |
188
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ASPDAC
2010
ACM
15 years 4 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
183
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ETS
2011
IEEE
14 years 6 months ago
2011
IEEE
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
184
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ISCA
2012
IEEE
13 years 9 months ago
2012
IEEE
Power consumption is a primary concern for microprocessor designers. Lowering the supply voltage of processors is one of the most effective techniques for improving their energy e...
187
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CODES
2008
IEEE
16 years 1 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
190
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ISCAS
2007
IEEE
16 years 1 months ago
2007
IEEE
—This paper presents a new context modeling technique for arithmetic coding of DCT coefficients in video compression. A key feature of the new technique is the inclusion of all p...