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ICCAD
2009
IEEE
119views Hardware» more  ICCAD 2009»
15 years 4 months ago
Iterative layering: Optimizing arithmetic circuits by structuring the information flow
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
ISCA
2005
IEEE
99views Hardware» more  ISCA 2005»
16 years 13 days ago
Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management
The importance of pushing the performance envelope of disk drives continues to grow, not just in the server market but also in numerous consumer electronics products. One of the m...
Sudhanva Gurumurthi, Anand Sivasubramaniam, Vivek ...
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
16 years 25 days ago
Crosstalk analysis using reconvergence correlation
Abstract— In the UDSM era, crosstalk is an area of considerable concern for designers, as it can have a considerable impact on the yield, both in terms of functionality and opera...
Sachin Shrivastava, Rajendra Pratap, Harindranath ...
208
Voted
ISPD
2010
ACM
224views Hardware» more  ISPD 2010»
16 years 1 months ago
An analytical placer for mixed-size 3D placement
Existing 3D placement techniques are mainly used for standardcell circuits, while mixed-size placement is needed to support highlevel functional units and intellectual property (I...
Jason Cong, Guojie Luo
184
Voted
DATE
2009
IEEE
102views Hardware» more  DATE 2009»
16 years 1 months ago
Register placement for high-performance circuits
—In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthe...
Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura