2778 search results - page 386 / 556 » Reuse Technique in Hardware Design |
191
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ISQED
2008
IEEE
16 years 1 months ago
2008
IEEE
Large-scale process fluctuations (particularly random device mismatches) at nanoscale technologies bring about highdimensional strongly nonlinear performance variations that canno...
108
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers....
168
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ISQED
2007
IEEE
16 years 1 months ago
2007
IEEE
Process related variations are considered a major concern in emerging sub-65nm technologies. In this paper, we investigate the impact of process variations on different types of c...
146
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GLOBECOM
2006
IEEE
16 years 27 days ago
2006
IEEE
— We present a field programmable gate array (FPGA) implementation of a turbo-like decoder for a serially concatenated pulse-position modulation (SCPPM) code. NASA developed thi...
167
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ISPD
2006
ACM
16 years 24 days ago
2006
ACM
Physical Design of modern systems on chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, e...