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» Reuse Technique in Hardware Design
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CODES
2006
IEEE
16 years 27 days ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...
ASPLOS
2008
ACM
15 years 8 months ago
Predictor virtualization
Many hardware optimizations rely on collecting information about program behavior at runtime. This information is stored in lookup tables. To be accurate and effective, these opti...
Ioana Burcea, Stephen Somogyi, Andreas Moshovos, B...
CLOUD
2010
ACM
15 years 12 months ago
Lithium: virtual machine storage for the cloud
To address the limitations of centralized shared storage for cloud computing, we are building Lithium, a distributed storage system designed specifically for virtualization workl...
Jacob Gorm Hansen, Eric Jul
CORR
2010
Springer
162views Education» more  CORR 2010»
15 years 7 months ago
Multi-standard programmable baseband modulator for next generation wireless communication
Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the soft...
Indranil Hatai, Indrajit Chakrabarti
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
16 years 7 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...