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» Reuse Technique in Hardware Design
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ISQED
2007
IEEE
165views Hardware» more  ISQED 2007»
16 years 1 months ago
On-Line Adjustable Buffering for Runtime Power Reduction
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream techn...
Andrew B. Kahng, Sherief Reda, Puneet Sharma
ICCD
2004
IEEE
126views Hardware» more  ICCD 2004»
16 years 3 months ago
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling
Simultaneous Multithreading (SMT) is emerging as an effective microarchitecture model to increase the utilization of resources in modern super-scalar processors. However, co-sched...
Joshua L. Kihm, Daniel A. Connors
DATE
2007
IEEE
91views Hardware» more  DATE 2007»
16 years 1 months ago
Transient fault prediction based on anomalies in processor events
Future microprocessors will be highly susceptible to transient errors as the sizes of transistors decrease due to CMOS scaling. Prior techniques advocated full scale structural or...
Satish Narayanasamy, Ayse Kivilcim Coskun, Brad Ca...
DSN
2007
IEEE
16 years 1 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
VEE
2006
ACM
116views Virtualization» more  VEE 2006»
16 years 23 days ago
Relative factors in performance analysis of Java virtual machines
Many new Java runtime optimizations report relatively small, single-digit performance improvements. On modern virtual and actual hardware, however, the performance impact of an op...
Dayong Gu, Clark Verbrugge, Etienne M. Gagnon