2778 search results - page 365 / 556 » Reuse Technique in Hardware Design |
171
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ASPDAC
2006
ACM
16 years 23 days ago
2006
ACM
- This paper presents an H.264/AVC baseline profile decoder based on a SoC platform design methodology. The overall decoding throughput is increased by optimized software and a ded...
141
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Networks-on-Chips (NoCs) are an emerging communication topology paradigm in single chip VLSI design, enhancing parallelism and system scalability. Processing units (PUs) connect t...
166
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ASYNC
2004
IEEE
15 years 10 months ago
2004
IEEE
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...
213
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
Designing cost-sensitive real-time control systems for safetycritical applications requires a careful analysis of the cost/coverage trade-offs of fault-tolerant solutions. This fu...
183
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ISLPED
2010
ACM
15 years 7 months ago
2010
ACM
The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This has raised urgent requirement for both...