2778 search results - page 361 / 556 » Reuse Technique in Hardware Design |
156
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
Placement migration is a critical step to address a variety of postplacement design closure issues, such as timing, routing congestion, signal integrity, and heat distribution. To...
200
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ISPD
2010
ACM
16 years 1 months ago
2010
ACM
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
152
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations...
131
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MICRO
2009
IEEE
16 years 1 months ago
2009
IEEE
As technology scaling drives the number of processor cores upward, current on-chip routers consume substantial portions of chip area and power budgets. Since existing research has...
177
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DATE
2008
IEEE
16 years 1 months ago
2008
IEEE
Failure Mode and Effects Analysis (FMEA) is a wellknown technique widely used for safety assessment in the area of safety-critical systems. However, FMEA is traditionally done man...