2778 search results - page 360 / 556 » Reuse Technique in Hardware Design |
187
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ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
139
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
Bounded model checking (BMC) has gained widespread industrial use due to its relative scalability. Its exhaustiveness over all valid input vectors allows it to expose arbitrarily ...
152
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HPCA
2003
IEEE
16 years 7 months ago
2003
IEEE
To sustain instruction throughput rates in more aggressively clocked microarchitectures, microarchitects have incorporated larger and more complex branch predictors into their des...
184
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ICCD
2007
IEEE
16 years 3 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
187
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...