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MICRO
2008
IEEE
138views Hardware» more  MICRO 2008»
16 years 1 months ago
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
Xi E. Chen, Tor M. Aamodt
VTS
2000
IEEE
89views Hardware» more  VTS 2000»
15 years 11 months ago
Fault Escapes in Duplex Systems
Hardware duplication techniques are widely used for concurrent error detection in dependable systems to ensure high availability and data integrity. These techniques are vulnerabl...
Subhasish Mitra, Nirmal R. Saxena, Edward J. McClu...
DFT
2008
IEEE
138views VLSI» more  DFT 2008»
16 years 1 months ago
Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsi...
Andrey V. Zykov, Gustavo de Veciana
PFE
2001
Springer
15 years 11 months ago
Introducing Product Lines in Small Embedded Systems
: How do you introduce product lines into a hardware dominated organization that has increasing software architecture awareness and products with extremely limited memory resources...
Christoph Stoermer, Markus Roeddiger
DAC
2008
ACM
16 years 7 months ago
Multiprocessor performance estimation using hybrid simulation
With the growing number of programmable processing elements in today's MultiProcessor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware...
Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer L...