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ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
16 years 22 days ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu
ISCAS
2005
IEEE
209views Hardware» more  ISCAS 2005»
16 years 11 days ago
Low complexity H.263 to H.264 video transcoding using motion vector decomposition
The H.264 adopts various block types and multiple reference frames for motion compensation. For transcoding a video sequence from the H.263 format to the H.264 format, it is benef...
Kai-Tat Fung, Wan-Chi Siu
VLDB
2005
ACM
180views Database» more  VLDB 2005»
16 years 7 days ago
Cache-conscious Frequent Pattern Mining on a Modern Processor
In this paper, we examine the performance of frequent pattern mining algorithms on a modern processor. A detailed performance study reveals that even the best frequent pattern min...
Amol Ghoting, Gregory Buehrer, Srinivasan Parthasa...
ERSA
2003
137views Hardware» more  ERSA 2003»
15 years 8 months ago
Next Generation Architecture for Heterogeneous Embedded Systems
The Software Communications Architecture (SCA), a mandatory specification for Software Radio implementations by the Joint Tactical Radio System (JTRS), defines a Common Object R...
S. Murat Bicer, Frank Pilhofer, Graham Bardouleau,...
WSC
2004
15 years 8 months ago
Implementing the High Level Architecture in the Virtual Test Bed
The Virtual Test Bed (VTB) is a prototype of a virtual engineering environment to study operations of current and future space vehicles, spaceports, and ranges. The HighLevel Arch...
José A. Sepúlveda, Luis C. Rabelo, J...