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FPL
2007
Springer
99views Hardware» more  FPL 2007»
15 years 10 months ago
Disjoint Pattern Enumeration for Custom Instructions Identification
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
Pan Yu, Tulika Mitra
ATVA
2004
Springer
138views Hardware» more  ATVA 2004»
15 years 10 months ago
Providing Automated Verification in HOL Using MDGs
While model checking suffers from the state space explosion problem, theorem proving is quite tedious and impractical for verifying complex designs. In this work, we present a veri...
Tarek Mhamdi, Sofiène Tahar
DATE
2004
IEEE
121views Hardware» more  DATE 2004»
15 years 10 months ago
Experiences during the Experimental Validation of the Time-Triggered Architecture
During last years, the Time-Triggered Architecture (TTA) has been gaining acceptance as a generic architecture for highly dependable real-time systems. It is now being used to imp...
Sara Blanc, Joaquin Gracia, Pedro J. Gil
HOTDEP
2008
168views Hardware» more  HOTDEP 2008»
15 years 9 months ago
A Spin-Up Saved Is Energy Earned: Achieving Power-Efficient, Erasure-Coded Storage
Storage accounts for a significant amount of a data center's ever increasing power budget. As a consequence, energy consumption has joined performance and reliability as a do...
Kevin M. Greenan, Darrell D. E. Long, Ethan L. Mil...
ATVA
2008
Springer
102views Hardware» more  ATVA 2008»
15 years 8 months ago
Time-Progress Evaluation for Dense-Time Automata with Concave Path Conditions
The evaluation of successor or predecessor state spaces through time progress is a central component in the model-checking algorithm of dense-time automata. The definition of the t...
Farn Wang