2778 search results - page 351 / 556 » Reuse Technique in Hardware Design |
158
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ICCAD
2008
IEEE
16 years 3 months ago
2008
IEEE
- In this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running...
162
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ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
169
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—This paper presents a technique to perform arbitrary fixed permutations on streaming data. We describe a parameterized architecture that takes as input n data points st...
166
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DATE
2008
IEEE
16 years 1 months ago
2008
IEEE
With the increasing levels of variability and randomness in the characteristics and behavior of manufactured nanoscale structures and devices, achieving performance optimization u...
183
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ISQED
2007
IEEE
16 years 1 months ago
2007
IEEE
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...