2778 search results - page 350 / 556 » Reuse Technique in Hardware Design |
138
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
Dual-execution/checkpointing based transient error tolerance techniques have been widely used in the high-end mission critical systems. These techniques, however, are not very att...
193
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CAV
2009
Springer
16 years 7 months ago
2009
Springer
We present the key ideas in the design and implementation of Beaver, an SMT solver for quantifier-free finite-precision bit-vector logic (QF BV). Beaver uses an eager approach, enc...
149
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ICCD
2007
IEEE
16 years 3 months ago
2007
IEEE
The cache hierarchy of state-of-the-art—especially multicore—microprocessors consumes a significant amount of area and energy. A significant amount of research has been devo...
173
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ICCD
2006
IEEE
16 years 3 months ago
2006
IEEE
This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction sc...
145
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ICCD
2004
IEEE
16 years 3 months ago
2004
IEEE
Formal and dynamic (simulation, emulation, etc.) verification techniques are both needed to deal with the overall challenge of verification. Ideally, the same specification/tes...