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» Reuse Technique in Hardware Design
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CAV
2007
Springer
129views Hardware» more  CAV 2007»
16 years 27 days ago
BAT: The Bit-Level Analysis Tool
Abstract. While effective methods for bit-level verification of low-level properties exist, system-level properties that entail reasoning about a significant part of the design p...
Panagiotis Manolios, Sudarshan K. Srinivasan, Daro...
163
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SPIN
2007
Springer
16 years 25 days ago
Scalable Multi-core LTL Model-Checking
Recent development in computer hardware has brought more wide-spread emergence of shared-memory, multi-core systems. These architectures offer opportunities to speed up various ta...
Jiri Barnat, Lubos Brim, Petr Rockai
IPPS
2006
IEEE
16 years 22 days ago
Investigation into programmability for layer 2 protocol frame delineation architectures
This paper presents the design and study of reconfigurable architectures for two data-link layer frame delineation techniques used for ATM and GFP. The architectures are targeted ...
Ciaran Toal, Sakir Sezer
ISCAS
2005
IEEE
98views Hardware» more  ISCAS 2005»
16 years 9 days ago
Integrated blind electronic equalizer for fiber dispersion compensation
This paper presents an adaptive blind electronic equalization technique for fiber dispersion compensation. Constant-modulus blind adaptive algorithm is proposed to provide referen...
Foster F. Dai, Shengfang Wei, Richard D. Jaeger
ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
16 years 9 days ago
A new CMOS wideband RF front-end for multistandard low-IF wireless receivers
—A wideband radio-frequency (RF) receiver front-end is designed in 0.18 µm CMOS technology with a new technique of linearization that makes the circuit suitable for operating at...
Igor M. Filanovsky, Md. Mahbub Reja, Ahmed Allam