2778 search results - page 344 / 556 » Reuse Technique in Hardware Design |
134
Voted
DATE
2006
IEEE
16 years 23 days ago
2006
IEEE
Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, vari...
206
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DATE
2006
IEEE
16 years 23 days ago
2006
IEEE
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
162
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DATE
2005
IEEE
16 years 10 days ago
2005
IEEE
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
176
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
141
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SIGOPSE
2000
ACM
15 years 11 months ago
2000
ACM
The algorithm for stabilising multiple stores, which we present in this paper, was developed in the process of designing the global stability and resilience mechanism for Grasshopp...